1. Field of the Invention
The present invention relates generally to an apparatus and method of maintaining the addresses of instructions in a processor pipeline. More particularly, the present invention relates to an apparatus and method of maintaining the address offsets of each instruction with respect to the address of a predetermined instruction within a set of instructions in a processor pipeline.
2. Description of the Prior Art
Every instruction executed by a microprocessor has an associated address that describes its location in memory. In a superscalar microprocessor such as the UltraSPARC microprocessor, up to four instructions may be executed simultaneously. With the possibility of up to four instructions being executed in every given clock cycle, four unique addresses associated with the four different instructions will have to be tracked when handling or executing unexpected procedural calls known as traps. When traps occur, the normal flow of execution of the instructions is interrupted and software codes for handling such traps are executed to handle the traps. After attending to the traps, the processor has to return to the point of interruption in the instruction stream, so that normal processing may continue.
In conventional microprocessors, traps typically result in a vectored transfer of control to supervisor software through a trap table. A trap may be caused by the presence of an exception, a trap instruction or an interrupt. When an exception occurs, the processor cannot continue executing the current instruction stream without software intervention. The exceptions are detected near the last pipeline stage right before the results of the instructions are written back to the processor register file. Thus, an exception can occur for any of the instructions within a set of instructions in the pipeline. For example, in an N-way superscalar microprocessor, instructions are dispatched in groups of one to N. If the youngest or most recent instruction in a group takes the exception, an address is needed for the instruction that is interrupted. In such a microprocessor, a large number of addresses in the instruction stream must be recorded so as to maintain the correct address for processing the trap, and so that program execution may be resumed following completion of trap processing. Thus, an N-way superscalar processor with P pipeline stages and 64-bit instruction addresses will have to store P.times.N 64-bit addresses. This involves the use of significant chip area and also impacts processor performance.
Accordingly, there is a need in the technology for an efficient means of tracking a series of addresses during processing and for maintaining the address associated with the specific instruction that was interrupted.
In addition, some microprocessors such as the UltraSPARC microprocessor are designed to store the address of the instruction that was interrupted and the address of the following instruction to be executed. In a microprocessor which utilizes pipeline processing, a number of sequential steps are involved from the beginning of the execution of an instruction until completion. Since a series of steps has to be executed between the beginning of execution of the instruction and the time that results are written back to the processor register file, there is a time lag between the occurrence of these two events. As a result, the addresses associated with the instruction have to be precisely tracked and maintained for each step.
Accordingly, there is a need in the art for an apparatus and method of efficiently and dynamically generating the addresses of each instruction in a microprocessor pipeline without having to store the address of each and every instruction in the pipeline, thus decreasing the required space on the chip and reducing processing time. In addition, there is a need in the technology for an efficient means for tracking and storing the addresses associated with the instructions in each process step in a processor pipeline.